The memory technology of computers has continuously been evolving in the interest of increased capacity as well as speed. New memory standards are often based on, and nominally compatible with, previous standards, but variations in memory bus protocol often limit the use of newer memory devices in existing computers. Upgrades of the CPU or memory controller hosting the memory may be required, and mixing of memory types on the same memory bus is often not possible, or results in degraded performance.
FIG. 1a shows an exemplary memory system 100 of a computer of the prior art, including a computing host (host) 102 connected to a memory bus 104 that is connected to memory modules 106. The host 102 may include a Basic Input Output System (BIOS) 108, and a memory controller 110 for managing the memory system. Numerous types of memory modules 106 are provided by the industry. At present we are concerned with Dual In-line Memory Modules (DIMMs) in general, and performance enhanced DIMMs in particular.
A DIMM is a module containing one or several Random Access Memory (RAM) or Dynamic RAM (DRAM) chips on a small circuit board with pins that connect it to the computer motherboard. A DIMM has a 240-pin connector and supports 64/72-bit data transfer. The memory devices of performance enhanced DIMMs are generally Synchronous DRAMs (SDRAMs), the terms DRAM and SDRAM being used interchangeably here.
A Registered DIMM (RDIMM) contains a buffer that is used to reduce the loading of the address and control signals on the memory bus.
Each of the memory modules 106 in FIG. 1a include memory devices 112 which are DRAMs; a Register Phase Lock Loop (RPLL) device 114 which is used to buffer a clock and control signals of the memory bus 104; and a Serial Presence Detect (SPD) Electrically Erasable Programmable Read Only Memory (EEPROM) 116 which is connected to the host 102 through a Serial Maintenance bus (SMBus) 118. The RPLL 114 regenerates the clock and bridges the control signals of the memory bus 104 (from the host 102) to a DIMM-internal bus to which the DRAMs are connected, and adds approximately one clock of latency to the control path.
The SPD EEPROM 116 (SPD device) stores specified timing and other parameters pertaining to the memory devices 112 that are located on the same memory module 106. It is typically only accessed by the BIOS 108 of the host 102 over the Serial Maintenance bus (SMBus) 118 during system initialization (booting) in order to automatically configure the timing of the memory bus 104 and the DRAMs 112.
Subsequently, timing of memory control and data signals is provided by the host 102, based on the information obtained from the SPD EEPROM 116 during a boot phase of the host, and the DRAMs 112 are programmed with computed latency values that are derived from the specified parameters where the computed latency values are derived from the specified parameters.
A Load Reduction DIMM (LRDIMM) is a high performance memory module which contains both the buffer for the control path in the RPLL, as well as a load reduction buffer for the data path. The load reduction function of the LRDIMM may be realised in one or more discrete Load Reduction Buffer (LRB) devices or may be performed in a modified RPLL (not shown in FIG. 1a).
Buffering in LRDIMMs results in the addition of at least one clock cycle delay in the control path (the same as in an RDIMM), but there is also delay added in the data path, which will cause a mismatch between the Data Queue Strobe (DQS) on the external memory bus, i.e. the memory bus 104, that carries the DQS signal between the host and the RDIMMs, and the strobe signal at the interface of the DRAM memory device within the LRDIMM. A solution for this problem may be found by changing the programming of the host 102, specifically of the BIOS 108. But no solution is known which would allow an LRDIMM to be used with an existing host without a changed BIOS.
A major issue with integrating LRDIMMs into a memory system that also includes RDIMMs, is that all DIMMs in a system are expected to have the same latency. If one DIMM is slower, then the other DIMMs all will be programmed with the longer latency by the host. The additional delay in the LRB causes a mismatch between the DQS on the memory bus and the buffered DQS at the DRAM within the LRDIMM.
It is evident that memory bus timing for LRDIMMs cannot be the same as for RDIMMs because of the added delay by the LRB in the data path. As a result RDIMMs and LRDIMMs cannot be used in combination on the same bus.
A solution may exist in a replacement or patching of the BIOS in order to permit a host to operate efficiently with LRDIMMs or compatibly with a mixture of DIMM types (RDIMM and LRDIMM) on the memory bus. However, this option is not readily available for existing computers that one may wish to upgrade to LRDIMMs.
Accordingly, there is a need in the industry for the development of an improved LRDIMM, a method for enabling efficient operation of LRDIMMs, and interoperation of RDIMMs and LRDIMMs without making changes to existing host controllers or to the BIOS.